Q=0, DZIE=0, SO=0, QIE=0, HDR=0000, DRE=0, VIF=0, QIF=0, VIE=0, V=0, DZIF=0, N=0, BUSY=0, DZ=0
Control/Status Register
| Q | Q flag: Accumulation Overflow 0 (0): No accumulation operation or accumulation operation does not overflow 1 (1): Accumulation overflows during a MAC instruction |
| V | V flag: Multiply or Divide overflow 0 (0): Calculation is not include divider or multiply, or the product/quotient does not overflow 1 (1): Product in multiply or multiply with accumulation, or quotient of a divide overflows |
| DZ | DZ flag: Divide by Zero 0 (0): For divide, the divisor is not zero, or the calculation is not divide 1 (1): For divide, the divisor is zero, which is a divide-by-zero error |
| N | N flag: Signed calculation result is negative 0 (0): Calculation raw result is zero or positive, or unsigned number 1 (1): Calculation raw result is negative |
| QIF | Q Interrupt Flag: Accumulation Overflow Interrupt Status 0 (0): No accumulation operation or accumulation operation does not overflow 1 (1): Accumulation overflows during a MAC instruction |
| VIF | V Interrupt Flag: Multiply or Divide overflow 0 (0): Calculation is not include divider or multiply, or the product/quotient does not overflow 1 (1): Product in multiply or multiply with accumulation, or quotient of a divide overflows |
| DZIF | DZ Interrupt Flag: Divide by Zero 0 (0): For divide, the divisor is not zero, or the calculation is not divide 1 (1): For divide, the divisor is zero, which is a divide-by-zero error |
| QIE | Accumulation Overflow (Q flag) Interrupt Enable 0 (0): Q flag (CSR[QIF]) set will not generate interrupt. 1 (1): Q flag (CSR[QIF]) set will generate interrupt to inform an accumulation overflow |
| VIE | Divide/Multiply Overflow (V flag) Interrupt Enable 0 (0): V flag (CSR[VIF]) set will not generate interrupt. 1 (1): V flag (CSR[VIF]) set will generate interrupt to inform a divide or multiply overflow |
| DZIE | Divide-by-Zero Interrupt Enable 0 (0): MMAU will not generate interrupt even CSR[DZIF]=1 1 (1): If CSR[DZIF] = 1, MMAU will generate an interrupt to signal a divide-by-zero. |
| DRE | DMA Request Enable 0 (0): MMAU will not generate DMA request when in IDLE (not busy) state 1 (1): MMAU will generate DMA request when in IDLE (not busy) state |
| SO | Supervisor-Only 0 (0): MMAU registers can be access in both User Mode or Supervisor Mode 1 (1): MMAU registers can only be access in Supervisor Mode |
| HDR | Hardware Revision Level 0 (0000): Current Hardware Revision Level is 0000 |
| BUSY | BUSY 0 (0): MMAU is idle 1 (1): MMAU is busy performing a divide or square root calculation |